`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/21 19:34:24
// Design Name: 
// Module Name: LightControl
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module LightControl(
    input   wire        clk,
    input   wire        rst,
    
    input   wire        i_en,
    input   wire [31:0] i_ctrl,
    output  wire [7:0]  o_out
    );
    
    reg [7:0] buffer = 8'b00000001;
    assign o_out = buffer;
    
    always @(posedge clk) begin
        if (rst == 0) begin
            buffer <= 8'b10000000;
        end else if (i_en) begin
            buffer <= i_ctrl[7:0];
        end
    end
endmodule
